Area and delay trade offs in fracturable LUT-based FPGA architectures

fracturable LUT-based FPGA architectures

Authors

  • Neeti Deenbandhu Chhotu Ram University of Science and Technology, murthal, Sonepat
  • Sunita Dahiya Deenbandhu Chhotu Ram University of Science and Technology, Murthal, Sonepat

Keywords:

Fracturable FPGA, Non-fracturable FPGA, Logic Blocks, look-up tables (LUTs)

Abstract

Now-a-days, most commercial Field- Programmable Gate Arrays (FPGAs) are based on fracturable look-up tables (LUTs). A fracturable LUT based FPGA can operate in two modes: one without shared input and other with shared inputs. This paper investigates area and critical path delay of 6-LUT based fracturable FPGAs for different cluster sizes and cluster inputs. It is found experimentally that compared to non-fracturable 6-LUT based FPGAs, the fracturable 6-LUT based FPGAs with cluster sizes 7 to 10 show significant improvement in the area-delay results, with different chosen values of cluster inputs.

URN:NBN:sciencein.jist.2024.v12.733

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Author Biographies

  • Neeti, Deenbandhu Chhotu Ram University of Science and Technology, murthal, Sonepat

    Department of Electronics and Communication

  • Sunita Dahiya, Deenbandhu Chhotu Ram University of Science and Technology, Murthal, Sonepat

    Department of Electronics and Communication,  Assistant Professor

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Published

2023-10-02

Issue

Section

Engineering

URN

How to Cite

Neeti, & Dahiya, S. (2023). Area and delay trade offs in fracturable LUT-based FPGA architectures. Journal of Integrated Science and Technology, 12(2), 733. https://pubs.thesciencein.org/journal/index.php/jist/article/view/a733

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