Early Register Transfer Level (RTL) power estimation in real-time System-on-Chips (SoCs)

Abstract

The present trend for low-power, smart-compact appliances for smart living has become a mandate that necessitate the demand for System-on-Chip (SoC) to embed more functionality on to a single chip. As feature size shrinks from 65nm down to 3nm, test power becomes a dominating parameter. It impacts many abstract hierarchical levels and takes several design cycles to analyze the issues very late in the netlist due to bottleneck of Scan-DFT (Design-For-Testability). Increase in power causes the SoC to toss for a re-spin or re-design and leaves few portions of the circuitry with hotspots which becomes irreparable. Thus, to bridge up this design estimation gap, it is important to realize estimation of design-power tradeoffs at early Register Transfer Level (RTL) rather than at gate-level implementation. This design test power estimation gap has been identified in this paper by performing early power analysis with power estimator tool on 14nm & 10nm real-time SoC designs. Clock & power gating optimization techniques and power intent profiles of design has been used for RTL to netlist estimation & correlation. It is found that less than 5% correlation was observed from RTL to netlist at partition level. Estimation error is (-11.50% to -7.56%) in 14nm to 10nm SoC when compared to estimation error of (-0.7% to -4.4%) in 65nm to 45nm.